1. Field of the Invention
This invention relates to computer architecture. In particular, the invention relates to processing units.
2. Background of the Invention
Digital processors are usually designed with a fixed word length to facilitate data handling and operation. The typical word length is a power of two and is compatible with memory data size. In many advanced processors, the word length is 32-bit, 64-bit, or 128-bit.
Although these traditional word lengths are useful for many scientific, data processing, business, medical, military, and commercial applications, they may not be convenient for applications where the word length may have any size depending on the type of information to be represented. Examples of such applications include network data processing and packet communications. In these applications, the data items may be represented by the minimum word size to optimize data transfers and switching. In addition, the word size may vary within the same processing unit. Furthermore, even when the data word sizes are comparable with the native word size of the processor, there are cases where blocks of data or long words are processed and these blocks of data may occupy at boundaries that are not aligned with the native word boundary.
Existing techniques to handle data with word sizes larger than the processor's native size are inefficient. These techniques involve execution of a large number of operations to shift and perform logical operations on the data items to be aligned or merged.